NVIDIA’s Marco framework innovates chip design with multi-AI agent

NVIDIA has introduced Marco Framework, a state -of -the -art approach that uses a graph -based work resolution and a multi -AI agent configuration that can be configured with a big step in developing chip design. According to NVIDIA, this innovative framework aims to deal with its unique complexity and long turnaround time (TAT) related to modern chips and hardware designs.

Marco Framework

The Marco Framework introduces a flexible system classified as a sub -task that is displayed in the graph node. Each edge of the graph means execution or knowledge relationship between these nodes, so dynamic and static work configuration is possible. This system supports both single and multiple AI agents in real time to integrate chip design knowledge such as circuits and timing.

In particular, the framework uses a tool such as Verilogcoder and RTLFIXER, using dynamic graphs for modifications between specifications and syntax errors, respectively. This framework also includes MCMM timing analysis agents, which showed significant efficiency improvements in debugging and analysis of timing reports.

HDL code generation power generation

One of the main applications of the Marco framework is the creation of the hardware description language (HDL) such as Verilog. As the complexity of VLSI design increases, it is difficult to create a phonetically functionally and functionally correct HDL code. The RTLFIXER of the Framework uses a search rag and a reaction prompt repeatedly responds to debugging and correct syntax errors, while VerilogCoder uses a task and circuit relationship graph (TCRG) to improve code generation and debugging processes.

Innovative DRC code creation

The DRC coder agent in the Marco framework is another highlight of creating a DESIGN Rule Check (DRC) code using multiple autonomous agents with vision functions. This agent interprets design rules of various formats to achieve the perfect F1 score when creating DRC code for advanced technology nodes, greatly reducing the time required for code generation.

Optimization and analysis

The Marco framework also improves standard cell layout optimization through LLM agents and optimizes layout PPA and debug pathways using natural language processing. In addition, the MCMM timing analysis agent uses dynamic work graphs for efficient timing report analysis to achieve remarkable speed compared to traditional methods.

Conclusion and future direction

NVIDIA’s Marco framework shows an innovative approach to chip design that enhances efficiency and performance by utilizing collaborative LLM -based agents. In the future, LLMs with high quality design data include education, debugging function improvement, and PPA metrics into design workflows.

To get additional insights to NVIDIA’s electronic design automation initiatives, you can explore the publications and projects of NVIDIA Design Automation Research Group.

Image Source: Shutter Stock